1. The Field of the Invention
The principles of the present invention related to differential transmitter circuitry; and more specifically, to a differential signal driver that may have either or both of complimentary and current-aided pre-emphasis for faster signal transitions, and that may act as either or both of a Low Voltage Differential Signal (LVDS) driver, or a Current Mode Logic (CML) driver.
2. The Relevant Technology
Electronic circuitry provides complex functionality that is proving ever more useful. Electronic circuitry pervades our modern lives in areas such as communication, entertainment, travel, productivity, and the like. One useful circuit is the differential signal transmitter.
Differential signaling offers several advantages over single-ended signaling. One is a significant reduction in Electro Magnetic Interference (EMI). Magnetic fields induced by one differential signal path tend to cancel out with magnetic fields induced by the other differential signal path. Differential signaling is also more resistant to negative effects of common mode noise. Differential signaling has been employed for some time.
More recently, Low Voltage Differential Signaling (hereinafter also referred to as LVDS) standards have been developed to employ differential signaling at higher throughputs and lower power than more traditional differential signaling technologies. There are many driver circuits that conventionally conform to the LVDS standards. In addition, Current Mode Logic (CML) drivers are used for high speed differential signal transmission.
As the speed of LVDS and CML differential transmission increases even now into the Gigahertz range, transmission losses (such as conduction or dielectric type losses) can have significant impact upon the ability to receive and properly interpret the transmitted signal. Because of such transmission loss, the eye diagram measured at the receive end closes in due to electronic dispersion effects as the line length and data speed increase. This makes it very difficult for receivers to recover the data.
Conventional differential LVDS drivers do incorporate some pre-emphasis to allow for sharper transitions from one differential signal output polarity to the opposite differential signal output polarity. Such sharper transitions at least partially compensate for transmission losses, thereby reducing the error rate or risk of error for the transmission.
FIG. 9 illustrates a conventional LVDS driver 900 that incorporates pre-emphasis. N-type Metal Oxide Semiconductor (NMOS) Field Effect Transistor (FET) 906 is a current source biased by input signals 901 (NB). The output differential voltage between output nodes 915 (PADMN) and 916 (PADMP) is a sum of two voltage drops: one across resistor 908 and one across resistor 909. By switching node 902 (RISE) and 903 (FALL) in the opposite direction, the direction of the current flowing through the two resistors is reversed, which changes the polarity of the differential voltage between output nodes 915 and 916.
For example, when the input voltage on node 902 is high (with the complementary voltage on 903 being low), NMOS FET (NFET) 914 is on and NFET 907 is off. In that case, current flows from supply 913 through resistors 912, 910, 908 and 909, NFET 914 and current source 906, and sinks into ground 905. The current creates a positive differential across output nodes 916 and 915. Conversely, when the input voltage on node 902 is low (with the complementary voltage on 903 being high), a negative differential is created between node 916 and node 915.
The differential voltage Vd across nodes 916 and 915 is equal to the effective resistance across those two output nodes multiplied by the current set by the bias NFET 906. Usually the effective differential resistance across nodes 916 and 915, which is determined by the values of resistors 908 through 912, needs to match the impedance of the transmission line. Thus, the effective differential resistance should not change significantly. Therefore, the differential output voltage Vd and its transition rate (also referred to as “edge rate”) is dependent only upon the bias current as the effective resistance is or needs be a constant. More specifically, the bias current (and thus the differential output voltage Vd) is dependent upon the size of the NFET 906 in a low voltage case such as this when the over drive voltage of the NFET 906 should be at relatively small value to keep it in saturation region with minimal drain to source voltage overhead.
As previously mentioned, as the transmitted differential signal travels through the transmission channel to the receiver, there is high dielectric transmission loss for high frequency components of the transmitted signals. To compensate for this, the LVDS driver circuit 900 has a pre-emphasis component for sharpening the edge transition. Specifically, this may be done by having a larger bias current thereby reducing switching time.
This cannot be accomplished by increasing the size of the NFET 906, since that would result in an increase in the steady state differential voltage. This could violate standards such as CML, and in particular low voltage standards such as LVDS. The lower voltage swing is one of the main grounds why LVDS or CML can operate at much higher speed than standard CMOS driver in the first place.
Typical implementation of the prior art on pre-emphasis is realized using NFET 918 and pre-emphasis signal 917 as shown in FIG. 9. The technique shown is what is being called current-assistant method. This method relies on turning-on the additional bias NFET 918 for just a short period time during the transition of the output from high to low or from low to high. The addition bias current gives a burst of higher driving current for this short period of time, and therefore boosts the edge of output waveform without an increase in static voltage swing. Dynamically, the voltage swing will have some overshoot or undershoot right after its transition completes and before it is completely settled out.
In this conventional technology, it is important to line up the controlling pulse 917 for pre-emphasis with the switching signals RISE 902 and FALL 903, to achieve edge emphasis during transition, and not distortion for steady state, of the output signal 915 and 916. This requires that the pre-emphasis signal should not arrive at node 917 before the data signals arrive at nodes 902 or 903. It is also important for the pre-emphasis signal 917 to conclude and thus turn off the transistor 918 before the signals at the output nodes 915 and 916 complete their transitions in order not to overshoot or undershoot the output signals.
Accordingly, what would be advantageous is a differential voltage signal driver circuit (such as a LVDS) driver circuit, or a Current Mode Logic (CML) driver circuit that operates at low voltage, and that uses effective pre-emphasis techniques that have controlled mechanisms for sharpening the transition of the differential output waveform, thereby facilitate higher data rate applications.